| On-the-fly multi-bit flip flop generation |
2023-5-08 |
2023-8-31 |
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| Transforming local threading resistance into global distribution resistance |
2023-2-15 |
2023-8-18 |
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| Interface level-shifter dual-rail memory architecture |
2023-2-08 |
2023-8-17 |
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| Fast waveform capture with low hardware footprint enabling full visibility |
2023-1-27 |
2023-8-03 |
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| Transforming a logical netlist into a hierarchical parasitic netlist |
2023-1-13 |
2023-8-17 |
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| Memory instance reconfiguration using super leaf cells |
2023-1-13 |
2023-8-10 |
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| Extended regular expression matching in directed acyclic graphs using predicate … |
2022-12-30 |
2023-7-04 |
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| Design for testability circuitry placement within an integrated circuit design |
2022-12-29 |
2023-6-29 |
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| Mask rule checking for curvilinear masks for electronic circuits |
2022-12-23 |
2023-9-05 |
2023-9-05 |
| Mask rule checking for curvilinear masks for electronic circuits |
2022-12-23 |
2023-4-27 |
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| SRAM Non-Clamping Write Driver with Write Assist |
2022-12-21 |
2023-6-29 |
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| Universal serial bus scheduling using real time data |
2022-12-19 |
2023-6-22 |
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| One-time programmable bit cell for front-side and back-side power interconnect |
2022-12-14 |
2023-6-16 |
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| Slack budgeting and discretization for a programmable device |
2022-12-13 |
2023-6-15 |
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| Creation of a reduced form model for scalable system-on-chip (SOC) level … |
2022-12-07 |
2023-6-09 |
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| Mask Synthesis Integrating Mask Fabrication Effects and Wafer Lithography … |
2022-11-10 |
2023-5-18 |
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| Transceiver devices with transmitter and receiver frequency control |
2022-11-04 |
2023-5-11 |
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| Embedded memory transparent in-system built-in self-test |
2022-10-31 |
2023-5-04 |
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| Computation of weakly connected components in a parallel, scalable and … |
2022-10-26 |
2023-5-04 |
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| Power supply tracking circuitry for embedded memories |
2022-10-14 |
2023-4-27 |
|
| Unified framework and method for accurate context-aware timing modeling |
2022-10-07 |
2023-4-13 |
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| Unified framework and method for accurate context-aware timing modeling |
2022-10-06 |
2023-4-13 |
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| Multi-protocol analog front end circuit |
2022-10-04 |
2023-4-13 |
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| Mask fabrication effects in three-dimensional mask simulations using feature … |
2022-9-30 |
2023-4-06 |
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| Mask fabrication effects in three-dimensional mask simulations using feature … |
2022-9-29 |
2023-4-06 |
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| Iterative generation of hypertext transfer protocol traffic |
2022-9-21 |
2023-3-23 |
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| Functional safety mechanisms for input/output (io) cells |
2022-9-16 |
2023-3-30 |
|
| Verification of Ethernet hardware based on checksum correction with cyclic … |
2022-9-16 |
2023-3-21 |
|
| Optical path tracing in an optical circuit design |
2022-9-09 |
2023-3-16 |
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| Trace buffer data management |
2022-9-07 |
2023-3-21 |
|
| Mask corner rounding effect in three-dimensional mask simulation using feature … |
2022-9-02 |
2023-3-03 |
|
| Supervised machine learning-based memory and run-time prediction using design … |
2022-8-31 |
2023-3-03 |
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| Detecting simulation, emulation and prototyping issues using static analysis … |
2022-8-26 |
2023-3-09 |
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| Memory optimization for storing objects in nested hash maps used in electronic … |
2022-8-24 |
2023-3-02 |
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| Routing of high-speed, high-throughput interconnects in integrated circuits |
2022-8-17 |
2023-3-02 |
|
| Low-Area, Wide Range Clocking Scheme using Inductance/Capacitance Oscillators |
2022-8-16 |
2023-3-02 |
|
| Clock multiplexer circuitry with glitch reduction |
2022-8-10 |
2023-2-16 |
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| Accounting for steady state noise in bit response superposition based eye … |
2022-8-08 |
2023-3-02 |
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| Overlapped inductor structure |
2022-7-28 |
2023-2-09 |
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| Boundary cell having a common semiconductor type for library cell |
2022-7-25 |
2023-1-26 |
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| Input/output devices that are compatible with gate-all-around technology |
2022-7-22 |
2023-2-01 |
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| Clock signal realignment for emulation of a circuit design |
2022-7-21 |
2023-2-02 |
|
| Unified power format annotated rtl image recognition to accelerate low power … |
2022-7-19 |
2023-2-09 |
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| Diagnosis of inconsistent constraints in power intent of an integrated circuit … |
2022-7-15 |
2023-1-17 |
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| Optimization of alternating büchi automata for formal verification of a circuit … |
2022-7-07 |
2023-1-19 |
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| Dividing a chip design flow into sub-steps using machine learning |
2022-7-05 |
2023-1-05 |
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| Scan chain compression for testing memory of system-on-chip |
2022-7-05 |
2023-1-10 |
|
| Scan chain compression for testing memory of a system on a chip |
2022-7-01 |
2023-1-05 |
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| Throughput efficient Reed-Solomon forward error correction decoding |
2022-6-29 |
2023-9-05 |
2023-9-05 |
| Length compensating waveguide for an optical circuit |
2022-6-24 |
2022-12-29 |
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| Machine-learning enhanced compiler |
2022-6-21 |
2022-10-06 |
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| Machine-learning-based power/ground (p/g) via removal |
2022-6-16 |
2023-1-16 |
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| Memory secure interface configuration |
2022-6-14 |
2022-12-16 |
|
| Placement and simulation of cell in proximity to cell with diffusion break |
2022-6-14 |
2022-9-29 |
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| Dynamic clock tree planning using feed timing cost |
2022-6-10 |
2022-12-13 |
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| Integrated circuit design and layout with multiple interpreters |
2022-6-08 |
2022-12-15 |
|
| Machine learning model for predicting detailed wiring topology and trajectory … |
2022-6-07 |
2022-12-23 |
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| Fail-safe software access licensing control on a per project basis without a … |
2022-6-03 |
2022-12-08 |
|
| D-type wholly dissimilar high-speed static set-reset flip flop |
2022-6-03 |
2022-12-08 |
|
| Dynamic clock tree planning using feedtiming cost |
2022-6-02 |
2022-12-15 |
|
| Machine learning for selecting initial source shapes for source mask … |
2022-6-01 |
2022-12-01 |
|
| Localization of multiple scan chain defects per scan chain |
2022-5-31 |
2023-8-29 |
2023-8-29 |
| Constraint file-based novel framework for net-based checking technique |
2022-5-31 |
2022-12-01 |
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| Large scale complex lithography using machine learning models |
2022-5-27 |
2022-11-29 |
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| Deterministic netlistic transformations in a multi-processor parallel computing … |
2022-5-26 |
2022-12-15 |
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| Transformations for multicycle path prediction of clock signals |
2022-5-26 |
2023-6-22 |
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| Identifying associations of security-related ports with their security … |
2022-5-25 |
2022-11-29 |
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| Parallel and scalable computation of strongly connected components in a circuit … |
2022-5-25 |
2022-12-08 |
|
| Non-functional loopback-paths removal from io-pads using logic replication |
2022-5-24 |
2022-12-01 |
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| Testable time-to-digital converter |
2022-5-24 |
2022-12-01 |
|
| Deterministic netlist transformations in a multi-processor parallel computing … |
2022-5-23 |
2022-12-08 |
|
| Non-functional loopback-paths removal from io-pads using logic replication |
2022-5-23 |
2022-12-01 |
|
| Enforcing mask synthesis consistency across random areas of integrated circuit … |
2022-5-20 |
2022-9-01 |
|
| Parallel and scalable computation of strongly connected components in a circuit … |
2022-5-19 |
2022-12-08 |
|
| Enhanced cell modeling for waveform propagation |
2022-5-19 |
2022-12-22 |
|
| Automation for functional safety diagnostic coverage |
2022-5-16 |
2022-11-22 |
|
| Layout Versus Schematic (LVS) device extraction using pattern matching |
2022-5-05 |
2023-5-30 |
|
| Modeling effects of process variations on superconductor and semiconductor … |
2022-4-29 |
2023-1-16 |
|
| Partitioning in post-layout circuit simulation |
2022-4-15 |
2022-8-18 |
|
| Multi-cycle test generation and source-based simulation |
2022-4-14 |
2022-10-20 |
|
| Runtime and memory efficient attribute query processing for distributed engines |
2022-4-01 |
2023-1-10 |
|
| Real time view swapping (rtvs) in a mixed signal simulation |
2022-3-31 |
2022-10-13 |
|
| Library design and co-optimization with circuit design |
2022-3-31 |
2022-10-18 |
|
| Accurate Calibration of Analog Integrated-Circuits Continuous-Time Complex … |
2022-3-30 |
2022-10-06 |
|
| Generating a reduced block model view on-the-fly |
2022-3-23 |
2022-10-13 |
|
| Multi-port multi-mode Reed-Solomon decoder |
2022-3-21 |
2022-9-27 |
|
| Propagating Physical Design Information Through Logical Design Hierarchy of an … |
2022-3-15 |
2022-9-22 |
|
| Incremental compilation for fpga-based systems |
2022-3-14 |
2022-9-22 |
|
| Independent skew control of a multi-phase clock |
2022-3-11 |
2023-5-16 |
2023-5-16 |
| Fast synthesis of logical circuit design with predictive timing |
2022-3-11 |
2022-9-22 |
|
| Isolating ion implantation of silicon channels for integrated circuit layout |
2022-3-08 |
2022-9-22 |
|
| Automatic design level identification and simplified reduced model generation … |
2022-3-02 |
2022-9-23 |
|
| Structural analysis for determining fault types in safety related logic |
2022-2-24 |
2022-9-01 |
|
| Causal ordering in graphs for faults in the design of integrated circuits |
2022-2-15 |
2022-8-30 |
|
| Message passing multiprocessor network for emulating vector processing |
2022-2-10 |
2022-8-16 |
|
| Correlating open source component matching results using different scanning … |
2022-2-08 |
2023-8-10 |
|
| Duty cycle adjustment circuit with independent range and step size control |
2022-2-02 |
2023-1-31 |
2023-1-31 |
| Reinforcement learning-based adjustment of digital circuits |
2022-1-19 |
2023-8-29 |
2023-8-29 |
| Asynchronous chip-to-chip communication |
2022-1-06 |
2022-7-21 |
|
| Hardware-based cyclic redundancy check recalculator for time-stamped frames on … |
2021-12-31 |
2022-8-09 |
|